1. Field of the Invention
The present invention relates to a thin film transistor (hereinafter, referred to as a TFT) formed over an insulating substrate such as glass, and a thin film integrated circuit including a plurality of TFTs, and a method for manufacturing the same.
2. Description of the Related Art
In order to realize high speed operation of a circuit, in a large scale integrated circuit (hereinafter, also referred to as an LSI) using a Si-wafer, a silicide is used for a source region, a drain region, and a gate electrode to lower resistance of the source region and drain region, and thus contact resistance is reduced. Salicide (Self Align Silicide) is known as a process for forming a silicide in a self-aligned manner with a diffusion layer of a MOS transistor (for example, Reference 1: Innovation of Logic LSI technology edited by Kenji Maeguchi, Masao Fukuma, Sotoju Asai, Science Forum pp. 238-241.)
FIGS. 5A to 5D each show a typical salicide process. This salicide process employs a two-step annealing method. First, a metal film 506 is formed to cover a MOS transistor including a diffusion layer 502, a field oxide film 503, a sidewall 504 and a gate electrode 505 that are each formed over a silicon substrate 501 (FIG. 5A). Ti, Co or Ni can be used for the metal film 506. As the metal film 506, TiN may be formed over the metal film to be used as an antioxidant film. After forming the metal film 506, first annealing is conducted to the MOS transistor (FIG. 5B). For the first annealing, RTA (rapid thermal annealing) is used in a nitrogen atmosphere at 600 to 750° C. in many cases. In the first annealing, a surface of the Ti film becomes TiN (not shown) due to a nitride reaction, and a metastable TiSi2 layer 507 is formed at the interface between silicon and the metal film 506. Next, TiN and an unreacted metal film 508 are selectively removed by a solution of H2SO4+H2O2+H2O or NH4OH+H2O2+H2O (FIG. 5C). At this step, since the TiSi2 layer 507 has relatively high resistance of about 60 to 300 μΩcm, annealing of about 800 to 850° C. is conducted twice to obtain a low-resistant TiSi2 layer 509 (15 to 25 μΩcm) (FIG. 5D). Since a silicide reaction is caused in TiSi2 by diffusion of Si, overgrowth of silicide on a sidewall is easily caused when the temperature of the first annealing is too high, and thus the gate electrode is easily short-circuited with the source and drain regions. Accordingly, the first thermal annealing is conducted at a temperature lower than the second thermal annealing to form a high-resistant phase TiSi2. After an unreacted metal film is removed, the second thermal annealing is conducted to form a low-resistant phase TiSi2.